The present invention relates to a method of manufacturing a semiconductor device and to a semiconductor device technique; and, more particularly, the invention relates to a technique which is effective when applied to a semiconductor device having a nonvolatile memory and a method of manufacturing the same.
An electrically rewritable nonvolatile memory, such as an EEPROM (Electrically Erasable Programmable Read Only Memory) or a flash memory, can perform on-board program rewriting. Consequently, the development period of a program can be shortened and the development efficiency can be improved. In addition, a nonvolatile memory is capable of various uses, such as in the production of a variety of products, each of which is low in volume, and is subject to changes for each destination and updating of a program after shipment. Particularly, in recent years, there has been an increasing need for a microcomputer having therein an MPU (Micro Processing Unit) and an EEPROM (or flash memory). As an electrically rewritable nonvolatile memory, an EEPROM whose floating electrode is made of normal polysilicon is mainly used. In an EEPROM having this structure, however, when there is a defect in a part of the oxide film surrounding the floating gate electrode, since the charge storage layer is formed of a conductor, all of the charges stored in a storage node may escape due to abnormal leakage. Particularly, with a further reduction in the size and an increase in the packing density, as is expected in the future, it is considered that this problem will become more conspicuous.
In recent years, attention has been given to an MNOS (Metal Nitride Oxide Semiconductor) structure and an MONOS (Metal Oxide Nitride Oxide Semiconductor) structure each having a nitride film (Si3N4 and the like) as a charge storage layer. In this case, charges contributing to data storage are stored in discrete traps in the nitride film, which serves as an insulator. Consequently, even if a defect occurs in a part of an oxide film surrounding a storage node and an abnormal leakage occurs, all of the charges in the charge storage layer do not escape. Thus, the reliability of data retention can be improved.
With respect to the configuration of a memory cell, a memory cell having a single transistor structure has been proposed. Proposed writing/erasing methods include a method of writing data by FN (Fowler-Nordheim) tunneling injection from a semiconductor substrate to the whole surface, a method of erasing data by passing FN tunnel current to the semiconductor substrate and, in addition, a method of writing data by injecting hot electrons and erasing data by passing FN tunnel current to the semiconductor substrate or source/drain regions. Further, in the case of an MONOS type single transistor cell structure, the structure is disturbed more easily as compared with an EEPROM cell structure, so that a split-gate type memory cell structure of a 2-transistor configuration having a control gate electrode also has been proposed. As split-gate memory cell structures of this kind, a structure in which a control gate electrode is provided over a memory gate electrode, a structure in which the memory gate electrode is provided over the control gate electrode, a structure in which the memory gate is provided over the control gate by using a side wall, and the like, can be realized in accordance with a process.
For example, Japanese Unexamined Patent Publication No. Hei 6 (1994)-85251 discloses a technique of forming not a memory cell, but a gate electrode of an MOSFET, and etching surface layer parts of a semiconductor substrate positioned on both sides of the gate electrode, thereby forming a step between a channel region and each of the source and drain regions (Patent Document 1).
Japanese Unexamined Patent Publication No. Hei 5(1993)-267250 discloses a technique, in a process of manufacturing a flash memory, of forming side walls on side surfaces of each of neighboring gate electrodes (floating gates) and partly etching a field insulating film provided as a lower layer and a semiconductor substrate by using the gate electrode and the side walls as a mask to thereby form a trench (Patent Document 2).
Japanese Unexamined Patent Publication No. 2000-91452 discloses a configuration in which offset side walls are provided on side surfaces on the channel side of an insulating film pattern over buried regions for a source and a drain of a memory cell transistor to thereby suppress expansion of the channel of the memory cell transistor so that data is not written/read to/from a not-selected memory transistor adjacent to a selected memory cell transistor when a nonvolatile memory having the MONOS structure operates (Patent Document 3).
Japanese Unexamined Patent Publication No. Hei 6 (1994)-125094 discloses a configuration in which an offset region is provided between an ONO film of a memory cell transistor and a gate electrode and a source region (Patent Document 4).
Japanese Unexamined Patent Publication No. 2001-168219 discloses a configuration in which a step is formed in a channel of a memory cell transistor having an MONOS structure, and channel hot electron injection is performed via the step. In the paragraph number 0038 in the publication, it is described that a gate electrode of a memory cell transistor from which charges are extracted by using FN tunnel current, thereby erasing data, is made of polysilicon, which is made conductive by being highly doped with p-type or n-type impurity (Patent Document 5).
Japanese Unexamined Patent Publication No. 2002-298591 discloses a configuration in which a threshold voltage of a memory cell is set to be higher than the lower one of the voltages applied to a source and a drain at the time of reading data, and is set to be lower than the voltage applied to the gate electrode at the time of reading data, in order to suppress or prevent the destruction of data when the threshold voltage of a not-selected memory cell increases due to repetition of a reading operation of an EEPROM (Patent Document 6).
[Patent Document 1]
Japanese Unexamined Patent Publication No. Hei 6 (1994)-85251
[Patent Document 2]
Japanese Unexamined Patent Publication No. Hei 5 (1993)-267250
[Patent Document 3]
Japanese Unexamined Patent Publication No. 2000-91452
[Patent Document 4]
Japanese Unexamined Patent Publication No. Hei 6 (1994)-125094
[Patent Document 5]
Japanese Unexamined Patent Publication No. 2001-168219
[Patent Document 6]
Japanese Unexamined Patent Publication No. 2002-298591